Magnetic (or magneto-resistive) random access memory (MRAM) is a non-volatile access memory technology that could potentially replace the dynamic random access memory (DRAM) as the standard memory for computing devices. Particularly, the use of MRAM-devices as a non-volatile RAM will eventually allow for “instant on”-systems that come to life as soon as the computer system is turned on, thus saving the amount of time needed for a conventional computer to transfer boot data from a hard disk drive to volatile DRAM during system power up.
A magnetic memory cell (also referred to as a tunneling magneto-resistive or TMR-device) includes a structure having ferromagnetic layers separated by a non-magnetic layer (barrier) and arranged into a magnetic tunnel junction (MTJ). Digital information is stored and represented in the magnetic memory cell as directions of magnetization vectors in the ferromagnetic layers. More specifically, the magnetic moment of one ferromagnetic layer is magnetically fixed or pinned (also referred to as a “reference layer”), while the magnetic moment of the other ferromagnetic layer (also referred to as “free layer”) is free to be switched between the same and opposite directions with respect to the fixed magnetization direction of the reference layer. The orientations of the magnetic moment of the free layer are also known as “parallel” and “antiparallel” states, respectively, wherein a parallel state refers to the same magnetic alignment of the free and reference layers, while an antiparallel state refers to opposing magnetic alignments therebetween.
Depending upon the magnetic states of the free layer (i.e., parallel or antiparallel states), the magnetic memory cell exhibits two different resistance values in response to a voltage applied across the magnetic tunnel junction barrier. The particular resistance of the TMR-device thus reflects the magnetization state of the free layer, wherein resistance is “low” when the magnetization is parallel, and “high” when the magnetization is antiparallel. Accordingly, a detection of changes in resistance allows a MRAM-device to provide information stored in the magnetic memory element, that is to say to read information from the magnetic memory element. In addition, a magnetic memory element typically is written to through the application of a bi-directional current in a particular direction, in order to magnetically align the free layer in a parallel or antiparallel state.
An MRAM-configuration integrates a plurality of magnetic memory cells and other circuits, such as a control circuit for magnetic memory elements, comparators for detecting states in a magnetic memory element, input/output circuits and miscellaneous support circuitry. The magnetic memory cells are designed to be integrated into the back end wiring structure of back-end-of-line (BEOL) CMOS methoding following front-end-of-line (FEOL) CMOS methoding.
To be useful in present day electronic devices, very high density arrays of magnetic memory cells are utilized in magnetic random access memories. In these high density arrays the magnetic cells are generally arranged in rows and columns, with individual cells being addressable for reading and writing operations by the selection of an appropriate row and column containing the desired cell. Also conveniently, orthogonal current lines are provided, one for each row and one for each column so that a selected cell is written by applying current to the appropriate row current line and the appropriate column current line.
Recently, and especially in view of modern portable equipment, such as portable computers, digital still cameras and the like, the demand of low-cost and particularly high-density mass storage memories has increased dramatically. Therefore, one of the most important issues for low-cost and high-density MRAM-devices is a reduction of the MRAM-cell size.
In their simplest embodiment, an MRAM-configuration comprising memory cells in a memory matrix between bit and word lines, in a completely ideal manner require only an area of 4F2 per information content or bit, where F denotes the minimum feature size of the technology used. Such configuration, however, will suffer from considerable parasitic currents flowing through adjacent memory cells during read-out on account of the only slight differences in the resistance values of the memory cells. In order to avoid this disadvantage more sophisticated configurations have already been envisioned, in which each individual memory cell contains an MTJ and a selection transistor. What is disadvantageous about this configuration, however, is that the advantage of a high-density configuration is lost. More particularly, since the bottom electrode of each MTJ has to be connected to the corresponding selection transistor through a succession of vias, contacts and metal landing pads, and, on account of the fact, that these landing pads need to have a large contact area with respect to minimum feature size F, as has been shown, in practical realization, there is no possibility to achieve a memory cell size below an area of 20–25 F2.
In order to resolve the above conflict between reduced area requirements in terms of minimum feature size F, on the one hand, and avoidance of parasitic currents, on the other hand, sharing of one selections transistor between several MTJs, for example, has been proposed. However, this solution may not be employed for MRAMs, since the storage signal cannot be mixed. Another solution, which has been previously proposed, envisions deep, especially self-aligned, vias running from the bottom electrode of the MTJ to the drain of the selection transistor, which, however, is a rather expensive technique, and, most likely will require long method development to be ready for mass production.